Full bridge PWM gate-driver motor control ICs have logic inputs

January 05, 2016 // By Graham Prophet
With a standard control interface for industrial and consumer applications, Allegro MicroSystems has added a family of full bridge gate-driver ICs designed to drive a wide range of DC brushed motors with simple logic from a microprocessor.

The A4955/56 and A5957 devices can support motor supply voltages up to 50V and load currents of up to 20A. These devices are targeted for both the industrial and consumer markets in applications such as robotic vacuum cleaners, vending machines, cash dispensing machines, coffee vending machines, ticketing machines, automatic gates and turnstiles, and sewing machines.

Flexible interface options are offered in three individual products, fitting existing designs with little or no firmware changes.

The A4955 offers parallel control inputs which drive the bridge in forward, reverse, brake, and standby modes; the A4956 offers phase, enable and mode inputs which drive the bridge in forward, reverse, brake and fast decay modes; while the A5957 offers phase, enable, and ‘sleep’ inputs which drive the bridge in forward or reverse modes with slow decay synchronous rectification.

Features of the A4955/56 and A5957 include an analogue output function which can be used to monitor current through an external sense resistor (if used). A sample-and-hold circuit is used to capture the peak voltage across the sense resistor and hold it during the ‘off’ time until the next PWM cycle begins. The voltage is amplified by a factor of ten and fed to the analogue output terminal, providing the user with the ability to accurately estimate the current in the load in real time.

Programmable gate drive allows an external resistor to set the magnitude of the current into the gates of the external FET bridge, allowing the user to control the slew rate of the driver to help achieve electromagnetic compliance.

Other features include internal pulse-width modulation (PWM) current control. Peak current is regulated with a fixed ‘off’ time PWM regulator, and the peak current is selected by the voltage on the reference voltage terminal. An overcurrent flag notifies the user when the device is actively PWM limiting the current in the load.