The addition of HiPer Simulation AFS to version 15.23 gives designers added capabilities for front-end design flow, including schematic capture, dual circuit simulators and waveform probing.
HiPer Silicon version 15.23 includes Tanner Analog FastSPICE (T-AFS), which integrates the Berkeley Design Automation Analog FastSPICE Platform with Tanner EDA's S-Edit schematic capture and W-Edit waveform analyzer. With HiPer Simulation AFS, two Spice simulators deliver the ultimate in performance and productivity, even for large netlists. T-Spice provides fast, accurate analysis while T-AFS delivers accuracy with runtimes 5x to 10x faster than traditional Spice simulators, on a single core. Users can drive the T-AFS simulator directly from S-Edit, getting the speeds and accuracy necessary for nanometer design. Simulation results are displayed automatically in W-Edit for viewing, measuring, and analyzing interactively.
Visit Tanner EDA at www.tannereda.com/tafs