Further details of FinFET ReRAM released

October 22, 2015 // By Peter Clarke
Some further details have been released of the resistive RAM made using a 16nm logic FinFET manufacturing process. A full paper is due to be presented on a 1-kbit memory array of such devices at this year's International Electron Devices Meeting (IEDM) coming up in December.

Paper 10.5, 1Kbit FinFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process, written by Hsin Wei Pan et al. of Tsing Hua University in Taiwan but also attributed to multiple authors from foundry TSMC.

The organizers of the conference have released diagrams that show a little more of the structure and that the memory does not require a separate specialized device to contain the hafnium oxide non-volatile memory. Instead each memory cell is based on three fins with the high-k layer used as the memory element.

Schematic at left shows the cell structure of the device, along with a view showing that the corners of the FinFET were contoured to enhance the electric field. Source: IEDM.

The images in schematic and transmission electron microphotograph appear to show the unit cell composed of two FinFETs with one used as the selector switch. The second is connected to word line but what remains unclear is whether the memory switch is contained in one or both of these FinFETs.

Next: TEM photograph