The tool automatically reads a netlist to identify and then generate key analogue design primitives including resistor arrays, current mirrors and differential pairs. HiPer L-Edit DevGen dramatically improves layout productivity and reduces design cycle time, while generating structures at a very high level of quality.
This month and exclusively for EETimes Europe readers, Tanner is offering a three-month license of HiPer L-Edit DevGen , worth 1500 euros, open to five companies. The suite contains the layout acceleration tool, plus the company’s layout editor (L-Edit) , along with additional features that include Interactive DRC (Design Rule Checking), Node Highlighting, Pad Map and Schematic-driven layout. Some of the key features of the tool include an easy integration with existing design flows with no change in methodology and unmodified schematics. The tool can be can be driven by any netlist through schematic driven layout (SDL) in L-Edit. It builds upon Tanner’s existing T-Cell architecture of parameterized cells that exist within L-Edit.ç
More information at: http://tannereda.com/products/layout-accleration
For what project are you likely to use this tool?
To qualify for the reader offer and get the chance to win one of these three-month licenses, complete the Reader Offer entry form below and tell us what project makes you interested in this package.