HAPS-DX includes optimised software for FPGA synthesis, debug and clock optimisation supporting fast prototyping modes to accelerate time to first prototype. Superior debug capabilities are built in with HAPS Deep Trace Debug, which can store seconds of signal trace data, and supports Synopsys Verdi, which delivers superior debug visualisation. Pre-validated DesignWare IP and access to a broad portfolio of HAPS daughter boards and FPGA Mezzanine Cards (FMCs) enables the quick assembly of prototypes. The Synopsys Universal Multi-Resource Bus (UMRBus) interface enables hybrid prototyping by providing a seamless connection between HAPS and Synopsys Virtualizer-based virtual prototypes for pre-RTL software development.
HAPS-DX is an FPGA-based prototyping system intended specifically to accelerate complex IP and subsystem prototyping. The HAPS-DX system, an extension of Synopsys' HAPS FPGA-based prototyping product line, includes customised synthesis and debug software to speed prototype bring-up and streamline the transition from individual IP blocks to full system on chip (SoC) validation. HAPS-DX offers up to four million ASIC gates of capacity and is plug and play compatible with the HAPS-70 series systems enabling a seamless prototyping solution from IP to full SoC for software development, hardware/software integration and system validation.
"Xilinx Virtex-7 X690T FPGA devices support 11.3 Gb/s SERDES data transfer rate, making them ideal for high bandwidth and high performance ASIC prototype designs," said Hanneke Krekels, director of test, measurement and emulation market segment at Xilinx. "Synopsys' HAPS-DX systems accelerate prototype bring-up via adoption of the industry standard FMC I/O technology supported by our Virtex-7 X690T FPGA, allowing designers to leverage hundreds of available FMCs, including analogue to digital/digital to analogue converters, video imaging and motor control."
The new, customised prototyping software included with HAPS-DX accelerates prototype availability through automated translation into a HAPS-DX specific implementation. New prototyping diagnostic and fast prototyping modes reduce the RTL review time and provide up to five times faster throughput than traditional FPGA synthesis tools. Time consuming tasks such as ASIC clock