Hi-rel 8 Mb SRAMs achieve zero soft-error-rate

December 12, 2014 // By Graham Prophet
Renesas has grown its Advanced Low-Power SRAM series, with the RMLV0816B and RMLV0808B devices, which have a density of 8 Mbits and are built with a fabrication process technology with a circuit linewidth of 110 nm.

In the Advanced LP SRAM Series, which can achieve soft-error-free and latch-up-free operation, Renesas started mass production of 4 Mbit products fabricated in a fine feature size process with a 110 nm circuit line width in December 2013 and now has launched the 8 Mbit products in this series. The new devices are high-reliability products that achieve the same soft error rate as Renesas' earlier products that were fabricated in a 150 nm process. They also achieve low-power operation with a standby current of maximum of 2 µA at 25°C, making them suitable for data storage in battery-backup devices.

Measures to deal with soft errors due to alpha rays and neutrons in cosmic radiation are seen as critical; since Renesas has added a capacitor to the memory node in the cell of the Advanced LP SRAM devices, these devices have an extremely high resistance to soft errors. A common method for dealing with soft errors is to correct the errors that occur using an ECC (error correcting code) circuit embedded in the SRAM or user system. There are, however, limits to such techniques, such as not being able to correct multiple bit errors depending on the performance of the ECC itself. To deal with this issue, the Renesas Advanced LP SRAM adopts structural measures that suppress soft error occurrence itself. The results of system soft error testing in Renesas currently mass produced 150 nm process Advanced LP SRAM has shown that these devices are essentially soft error free.

Additionally, the load transistors (p channel) in the SRAM cell are formed as polysilicon TFT devices, and since they are stacked in the upper layer of the n-channel MOS transistors that are formed on the silicon substrate, only n-channel transistors are formed on the underlying silicon substrate. As a result, there are no parasitic thyristor structures in the memory area and thus these devices have a structure in which latch-up cannot, in