High-level-synthesis boosted by faster verification flow

June 03, 2016 // By Graham Prophet
Calling it a major step in achieving C++/SystemC signoff, Mentor Graphics says the latest release of its Catapult Platform decreases the hardware design time from the design start to register transfer level (RTL) verification closure by 50% compared to traditional hand-coded RTL.

Existing High-Level Synthesis (HLS) methodologies, Mentor continues, improve design and verification productivity up to ten-fold; however, the time required to close verification on the resulting RTL can potentially wipe out these gains. This release of the Catapult Platform unifies HLS with an established verification methodology and new tools that enable rapid and predictable RTL verification closure based on C++/SystemC-level verification closure.


This latest Catapult release dds the Catapult formal-based C Property Checker (CPC) tool, which automatically finds bugs prior to synthesis, saving days or weeks of verification debugging time. CPC uses formal analysis to automatically identify and formally prove hard-to-find issues such as uninitialized memory, divide by 0, and array bounds errors in the users’ HLS C++/SystemC model (HLSM). In addition to automatic checks, CPC also formally proves user-written assertions and cover points which complement dynamic simulation providing comprehensive verification of the HLSM.


The latest Catapult release also facilitates easier, faster and more predictable RTL verification closure. It achieves this by removing RTL redundancies, adding new RTL test pins, and synthesizing user assertions and cover points in the HLSM into SVA (SystemVerilog Assertions). To reach functional coverage closure more quickly, Catapult also generates a complete RTL test environment that re-uses the user’s C++/SystemC testbench comparing to the original HLSM, to automatically verify that the simulation results are equivalent. To achieve 100% RTL structural/code coverage more quickly, Catapult works with the Questa CoverCheck tool in a seamless flow to quickly find and automatically generate waivers for unreachable code that can be safely ignored. For reachable code, the flow enables the user to quickly understand in generated waveforms what is needed for the HLSM to quickly close any remaining holes. This methodology enables verification to reach 100% RTL coverage closure in days after the HLSM is verified.


This release of Catapult HLS advances the standardization of the HLSM language by fully supporting the new Accellera SystemC Synthesizable Subset. In