The cores are effective for building systems requiring very high throughput-rate standard Ethernet connections, including chip-to-optical module, chip-to-chip, and backplane applications. The media access control (MAC) and physical coding sublayer plus physical media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba-2010 standard compliant, reducing design complexity for customers integrating 40GbE and 100GbE connections on the 28nm Stratix V and 40nm Stratix IV FPGAs.
“As more system designs use Ethernet at high speeds—not only for local-area network attachment but to interconnect within systems—subsystem IP, including 40GbE/100GbE MAC and PCS+PMA layers, becomes a vital component in the system design team’s toolkit,” said Vince Hu, vice president of corporate and product marketing. “These cores, optimized for integration with Altera development kits and Altera’s Quartus II software v12.0, create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs.”
With this development, Altera is enabling the system-level throughput promise of 40GbE/100GbE and raising the level of design abstraction for FPGA designers, while boosting design team productivity. The 40GbE and 100GbE MAC and PHY IP cores provide an interface composed of a single packet-based channel that is logically compatible with previous-generation Ethernet systems. The cores are supported in Altera’s Stratix V GT and GX FPGAs with transceivers operating at data rates up to 28.05 Gbps and 14.1 Gbps, respectively, and Stratix IV GT FPGAs with transceivers operating at data rates up to 11.3 Gbps. Stratix FPGAs combine high density, high performance and a rich feature set, allowing customers to integrate more functions and maximize system bandwidth.
The 40GbE and 100GbE IP cores are available for separate download from Altera.com and are compatible with the recently announced Quartus II software v12.0.