The tool is claimed to be 100x+ faster than Monte Carlo analysis. Memory IP is an integral part of SoC design, and requires low power, minimum cost and die area, and maximum performance at high yield. As a result, memory designers are early adopters of state-of-the-art foundry processes (28 nm and below). The increased variability associated with these new processes leads to increased risks in yield while meeting aggressive power, performance and area goals.
Many memory elements, such as bit cells and sense amps, are replicated in large arrays so that producing a single working product requires that the millions of repeated cells all work correctly, without failure. This makes high yield design a requirement; by definition, 5 sigma has only one failure in two million, and 6 sigma has only one failure in a billion. The number of simulations required to validate high yield using traditional methods is simply infeasible, even with today's fastest simulators, and even while utilizing massive compute clusters and cloud computing.
There is a continuing progression of electronic design automation tools to manage increased complexity through greater abstraction and partitioning methods. Meta-simulators are part of this trend. A meta-simulator feels like using a single simulator to the designer, yet drives hundreds or thousands of simulations in parallel from traditional simulation engines. Meta-simulators offer a “meta-level” analysis that may use a large number of simulations, while keeping the user input to not much more than a netlist. The output is simple, numerical, and well-defined, just like the result of a simulation.
Meta-simulation has historically been limited to simplistic methods, such as running corners or running Monte Carlo. Today, meta-simulation techniques can be much more powerful, addressing designer challenges and speeding up different analyses types in precisely-targeted ways. For example, rather than running 100 or 10,000 PVT corners just to search for the worst cases, a “Fast PVT” meta-simulator would analyze all the PVT corners and