High-throughput packet searches in FPGAs

July 03, 2013 // By Graham Prophet
Tabula and Algo-Logic have collaborated to release a second generation ternary search engine; the combination of Algo-Logic’s TSE2 and Tabula’s ABAX2P1 enables 600 million searches per second to process up to 400 Gbps of Ethernet packets in a single programmable device.

Tabula's solutions for high-performance programmable logic for network infrastructure systems now include an addition to its suite of high-performance packet processing solutions: the second generation Ternary Search Engine (TSE2) soft IP cores. This series of soft IP cores was developed by Algo-Logic for Tabula’s Spacetime architecture and is supported by Tabula’s Stylus compiler version 2.7.

Combined with Tabula’s ABAX2P1 device, the TSE2 core performs high-speed packet classification for customised search of Ethernet IPv4 and IPv6 packets. The core implements search functions critical to equipment such as firewalls, routers, flow controllers, VOIP management systems, L2 to L7 content matching engines, load balancers and software-defined networks (SDN).

"The combination of Algo-Logic’s highly scalable, customisable, small-footprint algorithmic search engines and Tabula’s ABAX2 P-Series devices’ multi-port memories enables wire-speed packet classification for multiple 100 Gbps streams. The integration of Algo-Logic’s cores on a 3PLD device is unique and provides an ideal way to implement Gateware Defined Networking features for wire-speed flow matching and programmable content matching in data centers.” said John Lockwood, CEO of Algo-Logic Systems.

The high-performance, customisable TSE2 matches header and payload data at 100 Gbps line rates with low, deterministic latency. Key performance metrics are: 150 million searches per second (MSPS) per core, scalable to 600 MSPS with four engines per device; large key-size widths of up to 640 bits (suitable for high N-tuple matching as described in the OpenFlow specification); comparable to a legacy CAM (content-addressable memory) capacity of 120 Mb (on-chip) to 7.6 Gb (with off-chip DDR3 memory), enabling usage in routers, switches, and network appliances; table sizes ranging from 512 fully associative to 12M exact flow match entries using DDR3 memory; low table lookup -latency of 256 nsec with on-chip memory, and 450 nsec with hybrid (on-chip plus DDR3) memory.

The TSE2 is composed of two 150 MSPS soft IP cores: associative ternary search engine (ATSE2), and exact match search engine (EMSE2). Both cores are highly flexible and