How to probe DDR4 with signal integrity? - Agilent offers an interposer

May 15, 2014 // By Graham Prophet
Agilent (soon to be Keysight) Technologies has introduced two interposer solutions for testing DDR4 and DDR3 DRAM designs with a logic analyser. They provide fast, accurate capture of address, command and data signals for debugging designs and making validation measurements.

The Agilent W4633A BGA interposer is used with Agilent E5849A probes for high-data-rate DDR4 x4 or x8 DRAM designs. The Agilent W3636A BGA interposer allows engineers to probe DDR3 x16 nonstacked DRAM more than 2 G deep.

As the industry transitions to DDR4 data rates up to 3.2 Gb/sec, engineers working on next-generation memory systems – such as those used in servers and embedded devices – face significant challenges. Probing and accurate signal capture are becoming increasingly critical for debug and validation of new designs.

Both interposer solutions provide direct access to the balls of the DDR4 x4 or x8 DRAM with low loading and minimal impact to signal integrity on embedded system design. The probe works in existing designs and eliminates the need for up-front planning or redesign. Both interposer solutions are designed to be used with the Agilent U4154A logic analyser system, tha Agilent claims as the fastest logic analyser with 4-Gb/sec state speed and 2.5-GHz trigger sequence speed.

The W3630A Series DDR3 BGA probes are used with oscilloscopes and logic analysers to perform physical-layer and functional tests for data rates up to 2400 Mb/sec with the U4154A logic analysis system. Features include;

· The B4622B DDR2/3/4 and LPDDR/2/3 protocol compliance and analysis toolset, which provides four different software tools: two for functional protocol compliance checks, one automated physical address trigger setup tool, and one tool that provides an overview of system performance through bus statistic information and a histogram view of address access.

· The B4621B DDR2/3/4 protocol decoder software, which translates acquired signals into easily understood bus transactions showing associated data bursts. Valid read and write commands are decoded to include row and column addresses and the complete data burst associated with the command. The B4621B bus decode software anticipates key system attribute inputs from default DDR2, DDR3 or DDR4 probing configurations or the DDR setup assistant tool to accelerate decode of DDR2, DDR3 or DDR4