How a wide choice of peripheral cells influences the performance and cost of analogue/mixed-signal ICs

November 03, 2014 // By Andreas Wild, ams
Skilled designers of an advanced analogue or mixed-signal ICs are constantly on the look-out for new ways to squeeze higher performance, lower power or lower cost out of the silicon fabrication processes available to them.

The common assumption is that real breakthroughs can only be made in big, once-in-a-generation shifts, such as a move from a larger process node to a smaller one. In fact, a comparable big effect can be achieved over time, through the accumulation of many small or incremental improvements. But the potential for such gradual improvement can easily escape notice, because it does not produce a sudden and dramatic change. All too often its importance is not recognised.

This article highlights one example of this. Complex analogue and mixed-signal ICs contain many IO (peripheral) cells which implement the device's signal and power interfaces to other components. Optimising peripheral cells can provide many small improvements which in aggregate have a big impact on the whole IC's performance and cost.

So how can designers take advantage of the opportunity for peripheral cell optimisation?

Improvements in peripheral cell libraries

The ongoing improvements in peripheral cell design are the result of continual research and development efforts undertaken by a range of organisations: analogue IC manufacturers, specialist analogue foundry service providers, and third-party providers of analogue and mixed-signal libraries and process development kits (PDKs).

The improvements stem in large part from the interactions that these specialist providers have with customers. In the field of high-performance analogue semiconductors, the most successful chip designs are the result of close collaboration between the IC’s developers, suppliers of analogue and mixed-signal IP, and a specialist analogue foundry.

Every IC developer benefits from the resulting accumulation by IP suppliers and foundries both of knowledge and of IP. In relation to the selection of optimised peripheral cells, this should be available to the chip design team in the form of:

- a comprehensive benchmark PDK, providing access to the peripheral cell IP supported by the designer’s chosen fabrication process (see Figure 1)

- engineering consulting services

A specialist analogue foundry or IP provider will have a much more extensive library of peripheral cell IP for analogue and mixed-signal ICs than a general-purpose foundry can offer. The development efforts in this direction by foundries and IP suppliers have been aimed in part at giving chip designers more choice, so that they can more closely match the specifications of the peripheral cell to the requirements of their design than they can if using a general-purpose foundry’s more restricted library.

But with choice comes complexity. This in turn means that an important function of the consulting service is to support the chip designers in their selection of the optimal IO cells.

Fig. 1: A foundry’s PDK provides a graphical user interface which helps the chip designer navigate through an IO cell library

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