HV optically isolated scope probe captures bridge-gate signals

January 16, 2017 // By Graham Prophet
Teledyne LeCroy’s HV fibre-optically isolated probe is presented as a route to measuring waveforms such as upper-side gate drive signals, floating control signals, or floating sensor signals. It offers 60 MHz bandwidth, 35kV common-mode isolation and up to 140 dB common-mode rejection ratio (CMRR).

 

The HVFO probe extends Teledyne LeCroy’s capabilities in the area of power electronics measurements; optimized for small-signal floating measurements on a HV bus in power electronics designs, it offers optical isolation between the probe tip and the oscilloscope input to reduce adverse loading of the device under test (DUT); and also reduces noise, distortion, ringing, overshoots, and transients on the measured signal. It surpasses the measurement capabilities and signal fidelity of both conventional HV differential probes and acquisition systems that rely on galvanic channel-to-channel and channel-to-ground high voltage isolation. It also avoids reliance on dangerous test setups that require floating the oscilloscope and probe, or investments in specialized isolated oscilloscope or data acquisition systems that result in other performance compromises.

 

To avoid the need for a separate power connection to the probe head while HV measurements are in progress, LeCroy has made the HVFO battery powered; up to 6 hours are available on a charge, and a single micro-USB alternately provides charging ans signal connection, to eliminate the possibility of an electrical connection being made when isolated measurements are in progress.

 

The HVFO architecture is, LeCroy says, simple, with a single laser and fibre optic cable providing optical isolation and modulated signal + data communication. Multiple tips achieve different operating voltage ranges, from ±1 to ±40V . The HVFO is small, to fit in tight spaces, with what LeCroy terms “just enough performance for real-world needs”.

 

Its primary target measurement scenario, the gate drive circuit in a power electronics design is a series RLC circuit with parasitic capacitances across the semiconductor device. An upper-side device has an applied gate voltage floating above ground. Any measurement probe with high tip capacitance in parallel with the parasitic capacitance from the gate to emitter (CGE) or gate to source (CGS), and/or high impedance and low loop inductance in series with the gate drive impedance, will at best undesirably load