I2C device interface IP needs zero programming, runs on FPGA

May 06, 2014 // By Graham Prophet
Polish IP company DCD (Digital Core Design) has created DI2CSB – an I2C slave base IP Core, a simple, efficient design that doesn’t need to be programmed. For deployment in FPGA or ASIC designs, the IP can work as a slave receiver or as a transmitter, depending on the working mode determined by the master device.

DCD’s DI2CSB IP Core is a two wire, bidirectional serial bus, which provides stable and efficient short distance data transmission between numerous devices. A very simple interface, composed with read, write and data signals, allows easy connection to target device. The DI2CSB is a technology-independent design, that can be implemented in a variety of both ASIC and FPGA technologies. It provides an interface between a passive target device e.g. memory, LCD display, pressure sensor etc., and an I 2C bus. The interface comprising read, write and data signals, allows easy connection to target devices. The core does not require anyprogramming and is ready to work after power up/reset. Read, write, burst read, burst write and repeated start transmissions are automatically recognised by the core. The DI2CSB core incorporates all features required by the I 2C specification and supports Standard, Fast, Fast Plus and High Speed transmission modes.

The DI2CSB can be customised to a project’s needs, such as for embedded microprocessor boards, consumer and professional audio/video, home and automotive radio, low-power applications, communication systems, cost-effective reliable automotive systems etc.

Features include;

Conforms to the latest I 2C specification

Slave operation

Slave transmitter

Slave receiver

Supports 3 transmission speed modes; Standard (up to 100 kb/sec), Fast (up to 400 kb/sec), and Fast Plus (up to 1 Mb/sec)

High Speed (up to 3.4 Mb/sec)

Allows operation from a wide range of input clock frequencies

Support for reads, writes, burst reads, burst writes, and repeated start

7-bit addressing

Fully synthesisable

Static synchronous design

Positive edge clocking and no internal tri-states

Scan test ready

Digital Core Design: http://dcd.pl/ipcore/121/di2csb/