The researchers first demonstrated reliable storage and moderate data retention of 2 bits/cell PCM, on a 64 k cell array, from room temperature (around 30ºC) to 80ºC and after 1 million SET/RESET endurance cycles. Under similar operating conditions, they then demonstrated the feasibility of 3 bits/cell PCM (eight levels of data encoding), with a chip consisting of a 2×2 Mcell array with a 4- bank interleaved architecture.
The memory array size is 2×1000μm×800μm and the PCM cells are based on doped-chalcogenide alloy, they were integrated into the prototype chip serving as a characterization vehicle in 90nm CMOS baseline technology.
"Reaching three bits per cell is a significant milestone because at this density the cost of PCM will be significantly less than DRAM and closer to flash", said Dr. Haris Pozidis, manager of non-volatile memory research at IBM Research and one of the authors of the paper presented at the IEEE International Memory Workshop in Paris.
The multi-bit storage capability relies on a set of drift-immune cell-state metrics and drift-tolerant coding and detection schemes.
IBM reports drift-tolerant multilevel cell PCM