With the new Verdi3 software, SpringSoft upgraded the underlying structure of its de facto industry standard fast signal database (FSDB) to both improve the raw speed of data retrieval and provide more efficient access mechanisms across the debug platform. Advancements include multi-threaded FSDB reader, new FSDB 5.0 format with compact file size, and parallel dumping of logic simulation results. In addition, a new robust SystemVerilog (Verilog-2009)-compliant language parser optimizes performance during SystemVerilog design and testbench debug operations with better error handling and multi-threaded incremental save capabilities that reduce compile time and memory utilization by as much as 30% and 75%, respectively.
The company has also rewritten the 'look and feel' of the Verdi environment with an entirely new Qt-based GUI that puts engineers in the driver seat. They can choose to deploy the Verdi software directly out of the box, simply re-configure the layout of Verdi desktop, or even build a custom cockpit for their SoC debug flows. Customizable toolbar, menu and hot key options provide a more natural fit with daily debug tasks. Additionally, new windows provide simultaneous access to multiple source files during debug operations, while ‘spotlight search’ enables faster, more efficient navigation of Verdi3 commands and features. Engineers can personalize the Verdi3 layout and debug modes for the way they want to work, while saving their preferences for the next or all future Customization includes the ability to change or create the functions and capabilities available to them as they go through the debug process. The new platform simplifies GUI-enabled integration of proprietary commands, third-party tools, and custom applications created by users of SpringSoft’s VIA Exchange. Engineers can traverse the Verdi design knowledge database, display relevant information, and execute VIA scripts directly from the GUI with seamless interoperability.
Visit SpringSoft at www.springsoft.com/verdi3