Imec overcomes a further barrier to IC fabrication below 10 nm

July 03, 2013 // By Graham Prophet
Imec has announced, at the Semicon West conference in San Francisco, that it has solved metallisation issues in advanced interconnects for the sub-1X technology node.

The Belgian research facility has developed a Manganese (Mn)-based self-formed barrier (SFB) process that significantly improves Resistance Capacitance (RC) performance, via resistance and reliability in advanced interconnects. It provides excellent adhesion, film conformality, intrinsic barrier property and reduced line resistance. This technology paves the way towards interconnect Cu metallisation into the 7nm node and beyond.

With continuous interconnect scaling, the wire resistance per unit length increases, which has a detrimental impact on the device performance (RC). Moreover, when reducing the dimensions with conventional barrier layers, an increased loss of copper (Cu) cross sectional area is observed, resulting in high resistance and decreased interconnect lifetime (the “wires” formed at such dimensions are prone to deteriorate through phenomena such as electro-migration and time dependent dielectric breakdown – EM and TDDB). To overcome these interconnect metallisation issues when scaling beyond the 1X technology node, imec’s R&D program on advanced interconnect technology explores new barrier and seed materials as well as novel deposition and filling techniques. The Mn-based SFB was demonstrated to be an attractive candidate for future interconnect technology. At module level, Mn-based SFB resulted in a 40% increase in RC benefits at 40 nm half pitch compared to conventional barrier and good lifetime performance (comparable to TaN/Ta reference).