Instruction tracing with Segger J-Link/J-Trace and Atollic TrueStudio

July 11, 2013 // By Graham Prophet
Segger’s J-Trace debug probe facilitates ETM instruction trace within Atollic TrueStudio (v4.1 and newer). If the target microcontroller has an internal trace buffer (ETB), this limited tracing also works when using any one of the J-Link/J-Trace models available from Segger.

ETM instruction trace allows the developer to look at the history of program execution. This is useful, for example, when a program crash is caused by an unexpected jump. In this case the developer can track back to where the program execution left the intended flow of the program.

“By adding instruction trace, Atollic’s TrueStudio becomes one of the top players in the tool-chain market for embedded systems”, says Dirk Akemann, Marketing Manager at Segger: “Segger is the leading provider of debug probes and the combination of Atollic TrueSTUDIO and J-Trace provides engineers market-leading debugging and programming tools”, says Magnus Unemyr, Atollic. “Additionally, the Segger debug probes enable the Atollic TrueVERIFIER unit test system, and the Atollic TrueANALYZER test quality measurement system, to test the embedded application in the target board, thus providing developers with an unrivalled tool solution for improving the software quality.”

J-Trace is the top model of the J-Link family adding instruction tracing capabilities using ARM’s Embedded Trace Macrocell (ETM). J-Trace models have an internal trace memory. Their direct interface to the ETM allows maximum trace frequency. The Segger J-Link debug probe is tool chain independent and works with commercial IDEs from: Atmel, Atollic, Coocox, Freescale, IAR, i-Systems, ImageCraft, KEIL, Mentor Graphics, Phyton, Rowley, Renesas, Tasking and others, as well as free GDB-based tool chains such as emIDE and EmBlocks. With the J-Link family, investments in the debug probe are likely preserved when changing compiler or even CPU architecture. J-Link supports multiple CPU families, such as ARM 7, 9, 11, Cortex-M0, M0+, M1, M3, M4, R4, A5, A8, A9 as well as Renesas RX610, 620, 62N, 62T, 630, 631, 63N; there is typically no need to buy a new J-Link or new license when switching to a different CPU family or toolchain. Adding support for additional cores in most cases only requires a software/firmware update.