Integrated PLL/VCO chips cut phase noise up to 9.8 GHz

March 07, 2016 // By Graham Prophet
Texas Instruments’ wideband RF phase-locked loops with integrated voltage-controlled oscillators offer frequency range of up to 9.8 GHz and best phase noise performance, to reduce system complexity.

LMX2582 and LMX2592 have a single-chip architecture to achieve a level of performance previously possible only through several discrete devices, TI aserts. The wideband devices support output frequencies of up to 9.8 GHz, allowing a single device to support various frequency bands in end applications including test and measurement, defence, microwave backhaul, satellite, and wireless communications equipment.

Features include;

- Optimised CO phase-noise performance: with 1.8-GHz carrier open-loop VCO phase noise of -144.5 dBc/Hz at 1-MHz offset, these devices are claimed as the first PLLs with integrated VCO to meet the multicarrier wireless GSM communication standard.

- PLL phase-noise performance: with lowest normalised PLL noise floor at -231 dBc/Hz and the highest phase-detector frequency of 400 MHz, the devices enable a very low integrated noise of 47 fsec RMS jitter. The devices meet the low noise floor requirements for clocking high speed data converters such as TI's RF sampling ADC12J4000.

- Expanded frequency range: eliminating the need for multiple narrowband devices, the LMX2592 supports 20 MHz to 9.8 GHz, and the LMX2582 supports up to 5.5 GHz, allowing designers to use one PLL for a range of wideband system designs.

- Improved spur performance: the devices' spur-removal technique can eliminate integer boundary spurs (IBS), enabling designers to improve channel density of their designs.

- Integrated architecture: Low-dropout regulators (LDOs) manage power-supply variations and improve noise immunity. A channel divider lets designers configure up to two differential outputs.


Evaluation modules, the LMX2592EVM and LMX2582EVM are available for $299. TI's WEBENCH Clock Architect online design tool simplifies the design process for a designer using the LMX2592 and LMX2582; the tool can recommend a single- or multiple-device clock-tree solution from a broad database of devices. It features PLL loop filter design, phase-noise simulation, and the ability for designers to optimise clock-tree designs.


LMX2592 and LMX2582 are available today in a 40-pin, 6 x 6-mm quad flat no-leads (QFN) package, for (LMX2592)