Integrating CCD and CMOS technology to improve CMOS imager performance

November 25, 2013 // By Graham Prophet
The imec nanoelectronics research centre is developing an embedded CCD in CMOS TDI image sensor for space applications

The device is a prototype of a high-performance, time-delay-integration (TDI) image sensor. The image sensor is based on imec’s proprietary embedded charge-coupled device (CCD) in CMOS technology. Imec developed and fabricated the sensor for the French Space Agency, CNES, which plans to use the technology for space-based earth observation.

The prototype image sensor combines a light-sensitive, CCD-based TDI pixel array with peripheral CMOS readout electronics. By integrating CCD with CMOS technology, imec says it has combined the best of both separate technologies. The CCD pixel structure delivers low-noise TDI performance in the charge domain, while CMOS technology enables low-power, on-chip integration of fast and complex circuitry readouts.

A TDI imager is a linear device that synchronises linear motion of the scene with multiple samplings of the same image, thereby increasing the signal to noise ratio. CCDs fit extremely well with the TDI application since they operate in the charge domain, enabling the movement of charges without creating excess noise. By combining the TDI pixel array with CMOS readout circuitry on the same die, imec produced a camera-on-a-chip or system-on-a-chip (SOC) imager, which reduces the overall system complexity and cost. The CMOS technology enables on-chip readout electronics, such as clock drivers and analogue-to-digital convertors, operating at higher speeds and lower power consumption than is possible with traditional CCD technology.


The prototypes were fabricated using imec’s 130-nm process with an additional CCD process module. An excellent charge transfer efficiency of 99.9987 % has been measured ensuring almost lossless transport of charges in the TDI array, and guaranteeing high image quality. Imec’s speciality imaging platform combines custom design (i.e., specialised pixels, high-performance readout circuits and chip architectures) with optimised silicon processing, such as dedicated implants and backside thinning, to achieve high-end specialised imagers.