The statement that the two companies have released does not provide a great deal of technical information, but this announcement appears to herald the commercialisation of phase change memory, in which the state of the 1-bit cell is determined by the resistance across a cell. Applying a low voltage to the cell allows its present value to be read; a higher voltage forces the cell to switch from one state (phase) to another: between higher or lower resistance states.
Phase change memories have been the subject of research for many years and have been a leading contender to provide the long-sought combination of speed, density and non-volatility that is desired to succeed DRAM and flash. There is a wide choice of materials available and researchers have sought to make the bi-state memory cell stable, repeatable in its transition, and manufacturable in conventional processes.
The structure that Intel/Micron outline is claimed to offer the necessary speed, to be manufacturable on a matrix layout with x-and y-oriented bit and word lines, and with a memory cell at each cross point – hence the name. Memory cells can therefore be individually addressed, giving freedom to write, erase or partition memory at any chosen level of granularity. “With a small cell size, fast switching selector, low-latency cross point array, and fast write algorithm, the cell is able to switch states faster than any existing non-volatile memory technologies today”, the companies say.
Further, layers of such cell arrays can be stacked (the ‘3D’ part of the name); the graphic accompanying the release appears implies that the (metal?) addressing lines that provide the top contacts to one ‘layer’ will also be address lines contacting the bottom of the next layer: if so, very high densities should be feasible while keeping process steps in reasonable limits. “The initial technology stores 128 Gb per die across two memory layers. Future generations of this technology can increase the number of memory layers, in addition to traditional lithographic pitch scaling, further improving system capacities,” the statement adds.
In saying that the memory, “significantly reduces latencies, allowing much more data to be stored close to the processor and accessed at speeds previously impossible for non-volatile storage” the two companies’ disclosure may also hint at significant amounts of non-volatile memory being fabricated tightly-connected to processor cores.
An obvious question, given the amount that Intel recently agreed to pay to acquire Altera is; If 3D XPoint memory is non-volatile: high-density: bit-wise re-writable: and long-endurance, as claimed – can you use it as the configuration memory of an FPGA in place of SRAM or flash? Beyond that, it would be possible to speculate on the possibilities of combination of FPGA, and processor cores plus large amounts of unified, close-coupled non-volatile memory acting as the repository of all of configuration, data and workspace.
Intel/Micron’s release provides minimal indication on the likely first market appearance of the technology, and does not say if the material ‘in production’ is early product, or test wafers: only offering that 3D Xpoint, “will sample later this year  with select customers, and Intel and Micron are developing individual products based on the technology.”
The text that follows (next page) is edited from the Intel/Micron text as-released;