Speaking at the IMEC Technology Forum here on Thursday (May 23) Keyvan Esfarjani, vice president technology & manufacturing at Intel and co-CEO of IMFT revealed some of the thinking behind IMFT's 3-D NAND strategy.
An industry-wide transition for the nonvolatile NAND flash memory technology from memory cells in a 2-D array to strings of NAND transistors integrated monolithically in the vertical direction is now anticipated. These 3-D memories are expected to be arranged as a 2-D array of vertical semiconductor channels with many levels of gate-all-around (GAA) structures forming the multiple voltage level memory cell transistors.
Toshiba is leading the charge towards 3-D NAND processes with its p-BiCS (pipe-shaped Bit Cost Scalable) technology, which it has presented at numerous learned conferences over several years. Towards the end of last year Toshiba announced that it had 16-layer devices based on a 50-nm diameter vertical channel. Samples are due this year and volume production in 2015. Toshiba's p-BiC technology arranges the transistor string in a U-shape.
But Esfarjani, while acknowledging there is a scaling limit for 2-D NAND flash, indicated in one of his slides that 2-D NAND flash can scale to two more nodes at about 15- and 10-nm. The slide showed that the first 3-D NAND generation is likely to be brought up alongside that 15-nm 2-D node. Esfarjani added that 16 layer NAND flash ICs will not be enough to provide an economic benefit. "You need 64 or at least 32 layers," he said.
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The transition to 3-D NAND according to Keyvan Esfarjani, vice president technology & manufacturing at Intel and co-CEO of IM Flash Technologies LLC, in a presentation at the IMEC Technology Forum.
Esfarjani said that the planar floating-gate high-K metal gate cell introduced by IMFT at the 20-nm node to replace a "wrap-around" cell used at 34- and 25-nm would scale further. IMFT introduced a 128-Gbit NAND flash memory at the 20-nm