The IP function; supports both line-out and power amplifiers; has an anti-pop-up-noise control signal; uses a spread-spectrum feature for safe integration with RF emitter/receiver; has a PLL-less design to prevent jitter issues on the DAC master clock; includes a jerk-less feature to prevent performance drop due to jitter on audio signal; and is delivered with advanced views enabling Noise Propagation Checks (NPC).
This stereo product has been designed to support most worldwide STB (set-top box) standards. Its flexibility makes the silicon IP also applicable for various applications such as docking station, digital radio or smart TV. sDACa-MT1.01 can reach performance of up to 105 dB of SNR, and its low silicon area at under 0.2 mm 2 at 55 nm combined with a low Bill-of-Material cost suit it fabricating a cost effective SoC targeting high volume markets.
The function is released at 55 nm but is easily retargetable over the range between 28 nm to 180 nm at TSMC and SMIC. Measurement reports on FPGA and silicon are available on demand.