IP builds FPGA-based MIPI interfaces to target video displays and cameras

September 09, 2014 // By Julien Happich
Developed with Xilinx' Premier Alliance members Northwest Logic and Xylon, the low cost Xilinx FPGA-based MIPI interface IP is optimised for cost sensitive video displays and cameras.

Xilinx' FPGAs can now be used to connect image sensors and ASSPs that support the MIPI Display Serial Interface (DSI) and Camera Serial Interface 2 (CSI-2) standards for the development of high bandwidth applications supporting 4K2K and beyond.

Northwest Logic provides a full range of DSI (Host and Peripheral) and CSI-2 (Tx & Rx) Controller Cores. These cores fully support 1-4 lane and 8 lane (dual 4 lane) MIPI operation. The cores are delivered fully integrated with the PHY logic to implement Xilinx’s low cost MIPI Interface technique.

Xylon, a provider of video processing IP cores, has taken a Xilinx FPGA Mezzanine Card (FMC), which implements the low cost MIPI Interface approach, Northwest Logic’s CSI-2 and DSI cores and its own cores running on an off-the-shelf Zynq All Programmable SoC evaluation board (ZC702 & ZC706) to create a comprehensive demonstration system.

The demonstration system takes a live video stream from an OmniVision CMOS sensor (OV16820), processes it in a Xilinx FPGA and then streams it to a MIPI-compatible display.

Xilinx;  www.xilinx.com

Northwest Logic;  www.nwlogic.com

Xylon;  www.logicbricks.com