DCD’s core enables a microcontroller to communicate with serial peripheral devices, but also to communicate with an interprocessor in a multi-master system. It supports all the features of SPI and transmission/reception FIFOs, to significantly reduce the CPU time.
The DSPI_FIFO system is flexible enough to interface directly with numerous standard product peripherals, even from different manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4. The clock control logic allows selection of clock polarity and choice of two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock. A serial clock line (SCK) synchronises shifting and sampling of the information on two independent serial data lines so the data is simultaneously transmitted and received.
The DSPI_FIFO automatically drives slave outputs (SS7O – SS0O) selected by the SSCR (Slave Select Control Register) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communication.
A write collision detector indicates when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow the DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
DCD’s IP Core is technology independent and silicon proven design. It is fully customisable, which means it is delivered in the exact configuration of a customer’s requirements. The DSPI_FIFO includes a fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.