Semtech says the Snowbush Platform IP has met the interoperability requirements of the HMC standard with significant margin and passed the rigorous testing required by Micron, co-founder of the Hybrid Memory Cube Consortium. This ensures compliance and enables system designers to deploy I/O designs that support the HMC standard on their ASICs and SOCs.
Semtech worked with Micron to perform silicon measurements on actual hardware to ensure that all the critical elements of this high-speed memory interface meet the requirements of the HMC specification. Such testing relieves ASIC or SOC developers – who use the IP – from conducting their own pre-silicon validation and encourages the early use of the interface on systems-level chips.
Micron supplies the HMC memory chips and Semtech will provide the Snowbush Platform IP to companies that will integrate it into their system-level chips to implement the high-speed link to the memory chip.
HMC is an approach to resolving the limitations of efficiency and power consumption imposed by conventional memory technology. With the ability to deliver up to 15 times the bandwidth of a DDR3 module, with 70% less energy and 90% less space than existing technologies, HMC's abstracted memory enables designers to devote more time to HMC’s features and performance and spend less time navigating the multitude of memory parameters required to implement basic functions. In addition, HMC manages error correction, resiliency, refresh and other parameters exacerbated by memory process variation.
“By supporting a new emerging standard such as HMC, with our silicon-proven 28nm IP platform, we continue to leverage and extend our programmable SerDes solution, which we pioneered over 10 years ago,” said Kevin Walsh, Director of Worldwide Marketing for Semtech. “The users of the HMC memory interface will benefit from our low power, low latency architecture, as this new form of serial memory emerges to deliver high data density per pin at very low power.”
Micron will begin volume production of