Xilinx defines and deploys Video over IP protocols for contribution and distribution networks with the provision of the SMPTE ST 2022-1,2 and SMPTE ST 2022-5.6 IP cores and reference designs. These cores encapsulate multiple compressed JPEG 2000 or MPEG transport streams (MPEG-TS), or uncompressed SDI streams onto 1 Gb and 10 Gb Ethernet IP networks, and offer optional forward error correction (FEC) to recover lost packets and provide robustness in media transmission.
Xilinx’s Video over IP cores and reference designs support the SMPTE ST 2022-7 seamless (hitless) protection switching standard and are available with Xilinx Kintex-7 FPGAs and Zynq-7000 All Programmable SoCs, using FPGA Mezzanine Cards (FMCs) from Xilinx Alliance Members, inrevium America and Faster Technology. Additional SMPTE ST 2022-compliant IP cores include a brand new high-channel count Video over IP Forward Error Correction (FEC) engine that handles up to 512 transport streams.
To address timing and synchronisation techniques based on the IEEE1588 Precision Time Protocol (PTP) over local and wide area networks, Xilinx has developed IP cores and reference designs that enable the distribution of video sync signals over IP networks, and generate clocks and timestamps for remote video sources. These IP cores and reference designs are also implemented in the emerging broadcast draft standards SMPTE ST 2059-1 and -2. Compliance for these new Video over IP cores and reference designs has been validated through the Video Services Forum Inc. (VSF), and is one of the development platforms used by the VSF that won the 2014 Emmy Award for Technology and Engineering for Standardisation and Productisation of JPEG2000 (J2K) Interoperability.
ST 2022-1,2,7 and ST 2022-5,6,7 cores are now available from Xilinx;
Reference designs for all cores, with application notes are at; www.xilinx.com/esp/broadcast/refdes_listing.htm