Iterated-map circuit creates chaos

August 11, 2016 // By Lars Keuninckx
The Design Idea circuit shown below.... is useful to show chaotic discrete-time dynamics to students, or as a random number generator.

The Design Idea circuit shown below is a simple implementation of an iterated unimodal map, reminiscent of the logistic or Verhulst map encountered in the study of nonlinear dynamics. It is useful to show chaotic discrete-time dynamics to students, or as a random number generator.


Specifically, the circuit implements:


Vk+1 = rF(V k)


where F is a nonlinear unimodal function (a “bump”), implemented by the circuit in the dashed box. The response of this circuit is shown in the Vout vs. Vin plot, Figure 1.



Figure 1. Response of the Q1 unimodal function circuit


r is a gain factor provided by U1b. U1a and U3a are simply buffers. During the low phase of the clock signal, the output voltage of the nonlinear function is stored on C1. When the clock switches to high, this voltage is transferred to C2, and then used as the next input to the unimodal function. The supply voltage is 12V. S3 (¼ 4066) is used as an inverter.



Figure 2. Schematic


For low gain settings ( r), the iterates have the origin, zero volts, as stable equilibrium: V* = rF(V*) . By increasing the gain, the circuit moves from a stable equilibrium to n-periodic oscillations. The iterates of an n-periodic oscillation can be seen as equilibria of the n-iterated map, e.g.,


V* = rF(rF(rF(V*)))


for 3-periodic oscillations. This is shown in the first oscilloscope screenshot, Figure 3, for r=4.7.



Figure 3. Behaviour for r=4.7 (red trace: Vk, blue trace: clock).


Further increasing the gain leads to chaos. Each initial condition or starting voltage in theory leads to a never repeating sequence of iterates. The logistic map


xn+1 = rxn(1-xn)


is the best known model for such an iterated chaotic system, and uses a parabolic function. However, it turns out that any unimodal map, including discontinuous