Lattice upgrades FPGA design software

February 01, 2013 // By Clive Maxfield
The folks at Lattice Semiconductor have just announced an array of advancements to their software platforms, debuting new versions of the Lattice Diamond and iCEcube2 design tools.

The updated software prominently features several notable advancements that improve power calculations and design productivity aimed at the creation of mobile and  consumer, communication, and industrial systems that undergo fast design cycles, demand power efficiency, and have aggressive cost constraints.

iCEcube2 Design Environment

“These refinements address the tough combination of power, size, cost, and connectivity requirements for such high-volume markets as smart phones, tablets, and mobile computing,’’ said Mike Kendrick, Director of Software Marketing at Lattice

“Fine-tuned for the unique architecture of our low power, low cost, low density and ultra-low density FPGAs, this software release marks a significant step forward in the design of power-sensitive devices. The tools enable an in-depth understanding of total power usage and simplify design exploration to achieve product goals faster than ever.”

Lattice Diamond 2.1
New Insights into Low Power Design

The updated Diamond Power Calculator contains a matrix that displays the power consumption of each block and each power supply. Also, the detailed power analysis for multiple design implementations can now be easily compared side by side in a new chart, extending the benefits of design exploration. For power- aware FPGAs such as the Lattice MachXO2 device, designers, designers can view the detailed power analyses for the two power modes side by side.  

Enhanced Design Exploration

Lattice Diamond software is designed to simply, create, and explore different design implementations to achieve the aggressive design goals of low cost, high volume designs. New algorithms further speed timing closure for multipass runs.  By dynamically fine tuning the netlist during placement to meet the characteristics of the device, innovative algorithms for the LatticeECP3 FPGA family achieve faster performance in the target device without incurring area penalties and increasing cost.  Moreover, timing reports now include enhanced information on unconstrained timing paths that accelerates the analysis of design constraints and timing results.

New Upgrades Boost Ease of Use
Lattice Diamond 2.1 software’s Hierarchy view is now automatically