LDPC Error Correction IP on FPGA, for flash-based data centre storage

August 11, 2015 // By Graham Prophet
Calling it “fundamental to enabling next generation flash-based applications for the cloud and data centre storage market” Xilinx has announced it will demonstrate Flash Memory Low-Density Parity-Check (LDPC) Error Correction LogiCORE IP at the Flash Memory Summit 2015*

As NAND Flash continues to advance with 3D NAND technologies, Xilinx notes that LDPC error correction is a critical core function for meeting the stringent reliability and endurance requirements of today’s storage solutions. Xilinx’s LDPC IP solution features code performance near the Shannon [theoretical] limit, achieves very low error floor, and supports both hard and soft decision decoding. The architecture is scalable and future proof to support various next-generation non-volatile memory devices and offers the high throughput and low latency required for the most demanding storage applications. This solution requires 50% less logic versus alternate solutions and is Xilinx FPGA optimised for smaller area and power.

“Xilinx has leveraged over a decade of error correction, DSP, and LDPC expertise to deliver a world-class LDPC solution for the data centre storage market and is currently the only FPGA vendor to do so,” said Dr. Chris Dick, Xilinx Chief DSP architect. “We’ve optimised the feature set of the LDPC IP to address the unique characteristics of flash and meet the cloud’s most demanding storage requirements.”

The Flash Memory LDPC Error Correction LogiCORE IP is available now for early access, with general availability to begin in Q4 2015.

Xilinx; www.xilinx.com/esp/datacenter/data_center_ip.htm

*Santa Clara, California, August 12-13, 2015; www.flashmemorysummit.com/