Leti's 5nm node to stack Si nanowires

December 09, 2016 // By Julien Happich
At the 2016 IEEE International Electron Devices Meeting (IEDM) held in San Francisco, researchers from CEA-Leti presented two papers unveiling promising nanowire architectural blocks for the 5nm node.

One of the papers, “NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs”, presents a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFETs. By using a novel methodology for the calculation of the surface potential including quantum confinement, the researchers claim the model is able to handle arbitrary NW/NS cross-section shape of stacked planar and vertical GAA MOSFETs (circular, square, rectangular), providing an excellent tool for design exploration.

Cross-sectional TEM image of stacked-NWs FET
after the integration of inner spacers.

This Nanowire Surface Potential (NSP) based model, they write, was validated both by numerical simulations and experimental data, which leads us to the second paper, "Vertically Stacked-Nanowires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain” demonstrating an actual physical implementation.

In this paper, Leti shares its finding on the very first functional devices featuring stacked-NWs transistors with integrated inner spacers to reduce parasitic capacitances and SiGe source drain (S/D) stressors to boost performance.

Both building blocks are required for the 5nm node, the researchers believe, which would extend the scaling limits of CMOS technology as a natural progression from FinFETs.

Visit Leti at www.leti.fr


Related articles:

IMEC reports nanowire FET in 'vertical' SRAM

Nanometric transistors take miniaturization into a new dimension

Beyond CMOS: exploring new roads and putting them to work

Moore's Law extended again?