Low-jitter clock functions for internet infrastructure and data-centre designs

August 01, 2014 // By Graham Prophet
Silicon Labs' Si534x are frequency-flexible clock solutions offering leading jitter performance for high-speed networking, communications and data centre equipment in Internet infrastructure.

Silicon Labs' next-generation “clock-tree-on-a-chip” portfolio includes high-performance clock generators and highly integrated multi-PLL jitter attenuators. These single-chip, ultra-low-jitter timing devices combine clock synthesis and jitter attenuation functionality to reduce the cost and complexity of optical networking, wireless infrastructure, broadband access/aggregation, Carrier Ethernet, test and measurement, and enterprise/data centre equipment including edge routers, switches, storage and servers.

Internet infrastructure and data centre systems are driving the need for a wide variety of clocks at different frequencies, signalling formats and voltage levels. Jitter performance requirements to support the highest data rates for 10/40/100G networks are also very demanding. Hardware designers, Silabs says, are often forced to use a costly and complicated combination of clock generators, jitter attenuators, oscillators and buffers to complete their clock trees. To address this industry need, Si534x jitter attenuators and clock generators deliver an efficient, cost-effective solution that combines all discrete timing functions into a single-chip clock IC solution.

Si5347/46/45/44/42 jitter attenuators and Si5341/40 clock generators provide an I2C-configurable platform with a combination of frequency translation capabilities and jitter performance of under 100 fsec RMS. By combining up to four independent jitter-attenuating PLLs and up to five ultra-low-jitter MultiSynth fractional synthesisers, the Si534x family is capable of generating up to 10 outputs with any combination of frequencies from 100 Hz to 800 MHz in a wide range of user-selectable output formats (LVPECL, LVDS, CML, HCSL and LVCMOS). This level of integration and frequency flexibility eliminates the need for multiple clock ICs, discrete level translation, loop filters and power supply filter components and significantly reduces bill of materials (BOM) cost and complexity while still providing more than 50% margin to stringent 10/40/100G jitter specifications.

Silicon Labs' also prvides ClockBuilder Pro software for high-performance clock configuration, settin up custom Si534x clocks for applications. Using the ClockBuilder Pro GUI, designers can generate sophisticated device configurations in less than five minutes, minimising software development overhead. The complementary ClockBuilder Go app for mobile