LTC6951 features four high performance current mode logic (CML) outputs, each equipped with an independent low noise clock divider and digital delay block to cover a frequency range between 1.95 MHz and 2700 MHz. With a total of 115 fsec RMS absolute jitter (SNR method), the LTC6951 delivers the low jitter clocks necessary to achieve the best SNR when clocking data converters with high input frequencies and fast output data rates.
The LTC6951 introduces three intelligent schemes to simplify output clock expansion and the creation of large clock trees employed in systems with multiple daughter cards or with a large number of data converters. Linear Technology’s EZSync output synchronisation method guarantees repeatable and deterministic phase relationships between all clock divider outputs on the LTC6951 and accompanying EZSync supporting devices. The ParallelSync multichip parallel synchronisation feature allows the outputs of multiple LTC6951 ICs to be retimed to the common reference clock. This permits reference aligned synchronisation in the reference clock domain with easy-to-meet nanosecond range setup and hold time requirements. The EZ204Sync JESD204B subclass 1 compliant synchronisation method builds on the previous two approaches and enables the generation of the SYSREF and DEVCLK signals essential to this JEDEC standard across multiple parallel connected LTC6951 ICs along with any other EZSync compatible clock devices.
Designing with the LTC6951 employs the LTC6951Wizard simulation and design tool, available for free download at www.linear.com/LTC6951Wizard. The LTC6951Wizard software provides appropriate PLL settings and loop filter component values with a click of a button, and accurately predicts the individual output’s phase noise and jitter. Besides performance simulation, the LTC6951Wizard GUI features a scope plot that simulates time domain results of the LTC6951 outputs based on the clock divider, delay and synchronisation settings, simplifying the design process and assisting in the circuit debugging phase.
90 fsec RMS Output Jitter (12 kHz to 20 MHz)
115 fsec RMS output jitter (ADC SNR method)