Fabricated by ST, the technology allows body-bias-voltage scaling from 0V to +2V: it decreases minimum circuit operating voltage and supports a clock frequency up to 460 MHz at less than 0.4V. The two partners presented a paper also describing 2.6 GHz clocking at 1.3V, as well as a demonstration kit.
The demonstrator achieves UWVR (ultra-wide voltage range), greater energy efficiency, and unprecedented trade-offs of voltage and frequency using a combination of design techniques, according to both ST and Leti who developed and optimised standard cell libraries to run over the 0.275-to-1.2V range. Among the optimised cells, fast pulse-triggered flip-flops are designed for variability tolerance at low voltage.
Additionally, on-chip timing-margin monitors dynamically adjust the clock frequency to within a few per cent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology.
As a result, even at 0.4V, the DSP exhibits a ten-fold increase in operating frequency compared to state-of-the-art competing solutions, according to both developers.
“This demonstration DSP shows that FD-SOI is blazing the trail for better portable and battery-powered products, using more efficient semiconductor chips, all the way down to the 10-nm node,” commented Philippe Magarshack, Executive Vice President, Design Enablement Services at STMicroelectronics.