Covering up to 1.34 GHz, the device integrates an ultra-low-noise “PLLatinum” fractional-N phase-locked loop (PLL) with a multicore voltage-controlled oscillator (VCO), enabling low phase noise and spurs, at a current drain of 39 mA (128 mW). The LMX2571 enhances radio sensitivity and dynamic range for applications such as low-power wireless communication, handheld oscilloscopes and signal analysers. An integrated frequency modulator enables the user to directly modulate the carrier to produce analogue frequency modulation (FM) or frequency-shift-keying (FSK), benefiting portable wireless applications such as land mobile radios, software-defined radios and wireless microphones.
The LMX2571 is also claimed to be the first RF synthesiser with an integrated feature to remove integer boundary spurs (IBS), allowing designers to eliminate spurious emissions and maximise use of radio channels in their wireless systems.
The LMX2571 RF synthesiser’s PLLatinum fractional-N PLL has a PLL noise figure-of-merit (FOM) of -231 dBc/Hz, eight times better than alternative devices which can benefit receiver sensitivity. An integrated FSK modulator with I ²S interface meets ETSI standards for wireless microphones and land mobile radios. Integration of low-dropout regulators (LDOs), a 5-V charge pump, and a fast transmit/receive (TRx) switch reduces bill of materials and solution footprint.
Engineers can evaluate the performance of the LMX2571 with the LMX2571EVM evaluation module (EVM), at $249.
TI's WEBENCH Clock Architect online design tool simplifies the design process for the LMX2571 as well as TI's other clock and timing devices. The tool can recommend a single- or multiple-device clock tree solution from a broad database of devices to meet system requirements. It features PLL loop filter design, phase noise simulation, and the ability for designers to optimise clock tree design for their performance and cost requirements.
The LMX2571 PLLatinum RF synthesiser, in a 6 x 6-mm quad flat no-leads (QNF) package, is $5.50 (1,000).