Lower Rx clock rate cuts EMI from LCD panel connections

February 10, 2014 // By Graham Prophet
Accepting a reduced pixel clock compared to existing devices, this LVDS receiver IC reduces EMI and power consumption in applications such as printers, copiers, appliances and digital cameras that use small LCD panels.

Texas Instruments’ LVDS receiver IC can use a a 4-MHz pixel clock in designs that employ small LCD panels. Compared to competitive devices, the SN65LVDS822 FlatLink LVDS receiver accepts a lower pixel clock, enabling 30% longer video transmission distance, with 60% fewer wires, to reduce electromagnetic interference (EMI) and power consumption. Its features include;

- pixel clock range of 4 MHz to 54 MHz to enable panel resolutions of 160 by 120 (QQVGA) to 1024 by 600 (WUXGA) at 60 frames per second (fps) with 24 bit-per-pixel (bpp) colour that, until now, required parallel LVTTL/LVCMOS interfaces.

- a reduced wire count results from support for both 4:27 and 2:27 deserialisation, providing the flexibility to further reduce wire count. The 2:27 mode with 14x sampling enables a 40% lane count reduction to two data lanes for systems with tight space constraints.

- flexible PCB layout and low EMI is assisted by a bus swap feature and reduced LVDS swing, while the 3-way selectable CMOS slew rate control reduces EMI by matching the slew rate with the needs of the application.

The LVCMOS output supports 1.8-V to 3.3-V CMOS signals

The SN65LVDS822RGZEVM evaluation module costs $99; the SN65LVDS822, in a 7 x 7 mm, 48-pin QFN package costs $2.81 (1000).

Texas Instruments; www.ti.com/sn65lvds822-pr