LPDDR4 PHY layer test added to Tek’s DDR solutions

September 23, 2014 // By Graham Prophet
Tektronix has announced the a complete PHY layer and conformance test solution for JEDEC LPDDR4, the next generation of mobile memory technology, to support high-speed, low-power memory interfaces for forthcoming mobile devices.

LPDDR4 builds on the current generation of LPDDR3 technology and will deliver improved data rates up to 4.26 Gb/sec and use an ultra-low voltage core to reduce power consumption by approximately 35% in mobile devices such as smartphones, wearables and tablets. The screenshot shows LP4 write-burst data eye analysis.

LPDDR4 introduces new test and measurement challenges due to lower input/output voltage of just 1.1V, higher data rates and compact mechanical designs that limit access to test points. There are also multiple changes in Vref, read burst and write burst which further increase the complexity to perform the tests mandated by the JESD209-4 specification. Tektronix provides a complete set of tools design to qualify LPDDR4 designs. Through automated set-up and test execution, it can reduce testing cycles from a week or more to a single hour.

"There's no question that LPDDR4 makes validation far more complex and challenging for the entire mobile memory ecosystem, from silicon vendors to system integrators," said Brian Reich, general manager, Performance Oscilloscopes, Tektronix. "We offer the test and measurement tools needed to efficiently bring this exciting technology to market, from high-performance oscilloscopes and probes to advanced analysis software spanning the entire memory validation continuum."

With this introduction, Tektronix now offers integrated PHY layer testing and debug of the new LPDDR4 standard in DDR-LP4 analysis software. By automating test setup and execution, DDR-LP4 gives memory designers the confidence that they are in full conformance with memory standards. Should a memory system fail conformance tests, designers can quickly switch to debug mode and use tools such as the Visual Trigger capability on Tektronix oscilloscopes to isolate events of interest for deeper root-cause analysis with the DPOJET Jitter and Eye measurement toolkit.

LPDDR4 interposers

In conjunction with Nexus Technology, Tektronix is also introducing LPDDR4 memory component interposers featuring two patented interposer designs. EdgeProbe interposers are designed for the demanding mechanical constraints required by mobile designs while socketed interposers are