The latest version of the Questa Verification Platform links simulation and formal verification capabilities to deliver X-value analysis and debug, which helps an IC design team avoid the risk of silicon and simulation failure. These new capabilities target both of the problematic effects of X-values that can lead to silicon bugs and wasted design effort: X-optimism and X-pessimism.
“Even though awareness of X issues is good, and designers do their best to follow coding guidelines to avoid X-state bugs, we still face the challenge of eliminating all X-related silicon bugs with traditional verification methods,” said Meng-Han Hsieh, director of Design Platform Division, MediaTek Inc.
“Within the Questa Platform we combine formal and simulation to obtain results that couldn’t be achieved with either of these technologies used independently,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “The X-value verification solution brings these complementary technologies together to help our customers overcome the risks of silicon and simulation failures caused by X-states.”
Simulation to Silicon Mismatches
Fundamental differences exist in the way that an X-value is interpreted in RTL simulation versus how it is treated by synthesis. The synthesis interpretation of X, as “don’t care”, can result in a silicon circuit that behaves differently compared to how it does in RTL simulation, where X is interpreted as unknown. Simply eliminating all X-values from RTL simulation is not practical, as not all storage elements in today’s large designs can be reset directly, especially those in the data path.
X-Optimism and X-Pessimism Verification with Questa
X-optimism is the more dangerous of the two risks associated with X-values, Mentor says. This effect causes unknown values to act as though they were deterministically known values in RTL simulation. This can mask bugs, since the design is not being simulated with all the signal values that it will experience in silicon.
The Questa Verification Platform now includes a mode with silicon-accurate semantics