Microsemi development kit hosts largest SmartFusion2 programmable device

October 01, 2014 // By Graham Prophet
Microsemi's SmartFusion2 parts feature programmable logic on the same die as an ARM processor core and a range of embedded logic functions; the Advanced Development Kit hosts the largest density, 150k logic element, part in the series.

With the SmartFusion2 150K LE System-on-Chip (SoC) FPGA Advanced Development Kit, board-level designers and system architects can develop system-level designs by using the two FPGA Mezzanine Card (FMC) expansion headers to connect a wide range of new functions with off-the-shelf daughter cards, which reduces design time and cost.

The 150 k-LE SmartFusion2 SoC FPGA is a low power device that integrates reliable flash-based FPGA fabric, a 166 MHz Cortex M3 processor, digital signal processing (DSP) blocks, static random-access memory (SRAM), embedded nonvolatile memory (eNVM) and high-performance communication interfaces.

The FMC headers connect a range of standard off-the-shelf daughter cards for applications such as image and video processing, serial connectivity (SATA/SAS, SFP, SDI) and analogue (A/D, D/A). The release of this kit also embodies IP in JESD204B, supporting the growing enterprise market for high speed data conversion for applications such as radar, satellite, broadband communications and communications test equipment.

Also included with the kit is a one-year platinum license for Microsemi's Libero SoC design software, valued at $2,500. Libero SoC has design wizards, editors and scripting engines that allow rapid development with SmartFusion2 and IGLOO2 FPGA-based designs.

The SmartFusion2 SoC FPGA Advanced Development Kit board has; PCIe x4 edge connector, two FMC connectors for developing solutions offered with off-the-shelf daughter cards, USB, I²C, two gigabit Ethernet ports, serial peripheral interface (SPI) and UART. A high precision operational amplifier circuitry on the board helps to measure core power consumption by the device.

The SmartFusion2 SoC FPGA memory management system is supported by 1GB of onboard double data rate (DDR3) memory and 2GB SPI flash:1GB connected to the microcontroller Subsystem (MSS) and 1GB connected to the FPGA fabric. The serialiser and deserialiser (SERDES) blocks can be accessed through the peripheral component interconnect express (PCIe) edge connector or high speed sub-miniature push-on (SMA) connectors or through on-board FMC connector.

Microsemi; www.microsemi.com/fpgaevaluationkit