Microsemi says it is the first field programmable gate array (FPGA) provider to offer a comprehensive software tool chain and intellectual property (IP) core for RISC-V designs. The company’s RV32IM RISC-V core is available for Microsemi’s IGLOO2 FPGAs, SmartFusion2 system-on-chip (SoC) FPGAs or RTG4 (radiation-tolerant) FPGAs, with an Eclipse-based SoftConsole integrated development environment (IDE) hosted on a Linux platform and the Libero SoC Design Suite providing full design support.
Microsemi’s RV32IM RISC-V core, developed in collaboration with SiFive, enables engineers to design with an open instruction set architecture (ISA), enabling complete portability and a more secure processor architecture governed by a permissive BSD license. RISC-V is an ISA which is now a standard open architecture under the governance of the RISC-V Foundation . RISC-V offers, Microsemi says, a ‘compelling’ soft processor solution for low power, reliable, secure FPGAs, “Now engineers can rely on an open ISA, without being tied to a single vendor and make use of open source tools and hardware. Never before has a processor allowed designers to inspect, modify, adapt, collaborate and migrate their design to the best platform for their product. Microsemi’s low power FPGAs with proven security and embedded flash are a natural fit for this new paradigm.”
“Our IGLOO2, SmartFusion2 and RTG4 devices are the ideal FPGAs to build RISC-V core onto, as we offer up to 50% lower power consumption with proven security for customers’ IP,” said Venki Narayanan, senior director of software and systems engineering for Microsemi’s SoC Products Group. “RISC-V is a great fit for implementing clean-slate processor capabilities for security, trust and reliability which are central to Microsemi’s solutions. We will continue our leadership position in this technology by further investing in this architecture to ensure customers have long-term roadmap support.”
The Libero SoC Design Suite is ready to implement the IP and, Microsemi adds, will efficiently pack [the core into] the FPGA logic elements (LEs),