Microsemi’s FPGA design software promises security, usability, efficiency boosts

March 14, 2016 // By Graham Prophet
The latest version of the FPGA maker’s design tools introduces secured production programming solution to protect against overbuilding, cloning and IP theft

Libero system-on-chip (SoC), version 11.7, is a suite of FPGA design tools for use with the company’s field programmable gate array (FPGA) products. The latest software release includes a number of new features to enhance ease-of-use and efficiency for designers, as well as advanced security and evaluation tools, for its RTG4 FPGAs, SmartFusion2 SoC FPGAs and IGLOO2 FPGAs.

 

According to a spokesman, “The release of our Libero SoC v11.7 software offers a significantly improved user experience due to a new and enhanced constraints flow with a new constraints management view, a fully redesigned ChipPlanner and a new simultaneous switching noise (SSN) analyser, ...[and]... an improved remote workflow installation and a Serialiser/Deserialiser (SerDes) BER calculator. Additionally, productivity has been greatly accelerated with a SmartTime UI that is two times faster and the SmartPower tool working five times faster in processing designs.”

 

Libero SoC v11.7 release also marks the production release of its Secured Production Programming Solution (SPPS) which is used to prevent overbuilding, cloning, reverse engineering, malware insertion and other security threats.

 

The release introduces an enhanced constraints flow aimed at simplifying the management of all constraints in a design. The solution is used to manage timing constraints, input/output (I/O) attribute constraints, floor planning constraints and netlist attribute constraints to ensure they can be created, imported, edited and organised in a single view. Timing constraints only need to be entered once, and can be automatically applied in synthesis, timing-driven place and route, and timing verification. Timing constraints for known hardware blocks and intellectual property (IP) elements are derived automatically.

 

The software release also features a fully redesigned ChipPlanner, a floor planning tool used to define and assign logic to regions within the FPGA. This design technique is particularly useful for controlling design placement in order to obtain optimal results. The new ChipPlanner also includes interface updates and significant runtime enhancements, most notably on large and highly-utilised designs.