Using this high bandwidth interconnect enables the baseband processor to access the application processor's dedicated DRAM memory for baseband processor operation, thus eliminating a separate, dedicated DRAM chip. Industry estimates translate the savings to an approximately $2 USD reduction in the total bill of materials for a smartphone. Board space is also saved, enabling mobile device manufacturers to reduce footprint.
"The LLI specification offers a significant advancement in mobile device system architectures," said Joel Huloux, Chairman of the Board of MIPI Alliance. "This specification opens the door to many design options. Our MIPI Alliance members continue to push the envelope of interface technology, benefitting all areas of the mobile ecosystem."
Improved data flow
The LLI interface specification targets low-latency cache refill transactions. Targets and initiators on the application processor and the baseband processor exchange transactions without software intervention — thus reducing latency. The specification also defines a best-effort traffic class, allowing access to remote memory-mapped peripherals without decreasing latency-critical traffic performance. Finally, the LLI interface allows for sideband signal transmission between the two chips, improving overall system communication.
The interface layers begin with an industry-standard physical layer. LLI leverages the MIPI Alliance M-PHY physical layer, a high bandwidth, widely-adopted approach used for peripheral inter-chip interconnects in many mobile and consumer applications. Upper LLI stack layers include a PHY adapter, data link layer and transaction layer.
Scalable, reduced design time
By using a common physical layer, the LLI specification offers a scalable solution accommodating existing and future requirements in mobile devices. Design configurations can leverage multiple transmission modes, enabling mobile device OEMs to customize their products based on customer needs. LLI also helps reduce overall system power by leveraging the M-PHY SLEEP and HIBERNATE power modes.
SoC designers can connect multiple chips in a "daisy chained" configuration, allowing the chips to share a single memory chip. This enables designers to pursue a multi-chip platform approach, where feature sets can be modified