The CSI-2 (Camera Serial Interface) transmitter IP core is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs packing in form of CSI-2 long packets and short packets, and sends them via PPI interface to the Host processor. HDL Design House CSI-2 Tx IP core can be combined with CSI-2 Rx and D-PHY IP cores, also available from the FlexIP core library, thus providing a complete, single-vendor MIPI CSI-2 solution. HIP 3900 is compliant with the following specifications: CSI-2 (Camera Serial Interface) version 1.01, D-PHY version 1.0, AMBA3 AHB-Lite Protocol Specification version 1.0. The AHB interface is used for configuration of the CSI-2 transmitter IP core, allowing external access to the core's 32-bit configuration, status, power management, and interrupt registers.
The PPI interface is used to transmit pixel and command from external D-PHY, using independent High Speed (HS) and Low Power (LP) TX data paths. When in LP mode, the CSI-2 Transmitter IP core is used for Ultra Low Power control. In HS mode, the data is received using between 1 and 4 data lanes. The Camera Pixel Interface is used to directly connect Camera sensor with CSI-2 Transmitter IP Core. HIP 3900 offers more than 30 configurations and interrupt registers. It supports up to 4 data lanes, one clock lane and up to 4 virtual channels, as well as high speed, low power and ultra-low power modes. It supports various pixel formats defined in CSI protocol version 1.01: YUV420 8-bit, YUV420 8-bit (legacy), YUV420 10-bit, YUV422 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit (CSPS), YUV422 8-bit, YUV422 10-bit, RGB888, RGB666, RGB565, RGB555, RGB444,RAW6, RAW7,RAW8, RAW10, RAW12, RAW14. The MIPI CSI-2 Transmitter IP core is available now in 65nm and 40nm.
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