New to version 2012.02 of Riviera-PRO are support for the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. This last aspect also makes Riviera-PRO an ideal platform for working with the Open Source VHDL Verification Methodology (OS-VVM).
With release version 2012.02 it is now possible to log class objects and display them in Riviera-PRO’s Waveform Viewer; elevating the EDA tool’s debugging capabilities to a new level. This feature makes possible the analysis of dynamic objects over time, organically combined with the objects of any other data type. It is also possible to log Information, Warning and Error messages; generated during simulation runtime in conjunction with appropriate markers displayed directly in the Waveform.
Shipping with UVM 1.1a – i.e. the latest version of the industry-standard SystemVerilog-based verification library - Riviera-PRO 2012.02 product release features multi-threaded SystemVerilog compilation (which is circa 25% faster on a typical UVM-based testbench) reduced compiler ‘noise’ (to ensure clean and concise logs) and new environment variables that facilitate the use of the UVM library itself and make scripting much easier.
Regarding languages, this product release enables a number of new constructs for:
SystemVerilog - constructs such as forward typedef, extern module declarations and dynamic arrays in constraint blocks;
SystemVerilog Assertions (SVA) - constructs such as multi-clocked properties and sequences, so a great benefit to engineers working on multiple clock domain designs; and
VHDL - constructs such as the ‘force’ and ‘release’ signal assignment statements.
Riviera-PRO release version 2012.02 also delivers enhancements to the tool’s HDL Editor and Waveform Viewer, further boosting its value as a versatile script-based, design, (common-kernel) simulation, analysis and debug environment for FPGA and ASIC designers.