Modern design tools facilitate tuning DDR4 signal paths

February 03, 2015 // By Ben Jordan, Altium
Adjusting the lengths of signal tracks so that the delays are matched and meet the DDR4 specification would be an almost impossible task without modern design tools.

The latest standard in the race for ever-denser and ever-faster dynamic RAM is DDR4, short for double data rate, fourth-generation synchronous dynamic random-access memory. DDR4 memory will operate at speeds between 1600 MHz and 3200 MHz, compared to speeds between 800 MHz and 2400 MHz for DDR3 memory. Standard memory modules will be denser, too. The DDR4 standard specifies DIMMs up 128 Gbytes, compared to a maximum of 16 Gbytes for a DDR3 DIMM.

DDR4 modules employ a hybrid topology. DDR4 designs have parallel, length-matched transmission lines for the data bus and daisy-chained, length-matched transmission lines for the clock, address, and control bus lines. The latter type of topology is sometimes called "fly-by" topology. Each signal is routed sequentially from one device to the next and is then terminated after the last device.

This topology eliminates reflections, but the downside is that the signal delay increases for each successive device in the chain. However, this topology can be used when the output device can compensate for this signal skew, using a technique known as "signal levelling."

Figure 1 shows how an address or control line would be routed to each of the SDRAM devices on a DDR4 dual-inline memory module (DIMM). The lengths of the bus connections from connector to first device, and from device to device, must be tuned so that commands arrive at each chip centre-aligned to the clock. The DDR4 specification spells out the timing requirements for each of the segments of this address or command line. Each segment must be treated as a transmission line, which is why the segments are designated as TL0, TL1, etc.

Figure 1. DDR4 DIMMs use a 'fly-by' topology for address and control lines.


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