It provides a number of advantages including a customizable interface for unique customer applications and a FPGA-based design for long-term product lifecycle management. TMPE633 module versions are available with either 26 ESD-protected 5V-tolerant TTL lines, 13 differential I/O lines with EIA 422/485 compatible ESD-protected line transceivers or 13 differential I/O lines using Multipoint-LVDS transceivers.
All I/O lines are individually programmable as input or output. TTL I/O lines can be set to high, low, or tristate. Each TTL I/O line has a pull-resistor to a common programmable pull-up voltage that can be set to +3.3V, +5V and GND. Differential I/O lines are terminated, RS-485 lines with 120Ω and M-LVDS lines with 100Ω. The I/O signals are accessible through a 30 pin Pico-Clasp latching connector.
The User FPGA is configured by a SPI flash. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”). With TEWS’ TA308 Programming Kit, direct JTAG access to the FPGA is possible using the Xilinx Platform Cable USB. User applications for the TMPE633 with XC6SLX25T-2 FPGA can be developed using the design software ISE WebPACK which can be downloaded free of charge from www.xilinx.com
TEWS offers a documented basic FPGA Example Application design. It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TMPE633. It implements local bus interface to local bridge device, register mapping and basic I/O. It comes as a Xilinx ISE project with source code and as a ready-to-download bit stream.
In order to support long term programs, the TEWS’ modules have a 5 year warranty.
Tews Technologies is a provider of embedded I/O and CPU products based on open architecture standards such as PMC, XMC, IndustryPack (IP), CompactPCI, standard PCI, PCIe, mPCIe, AMC, FMC, and VME; www.tews.com