Its Full TCP Offload is fully compliant with IEEE802.3 specifications and required RFCs of the TCP/IP protocol. It uses Streaming FIFO interface for data and configuration is done via industry standard AXI/PLB and other CPU Interfaces that allow seamless drop-in integration with Altera, Xilinx, Tabula FPGA devices and ASICs.
The Nano-TOE IP-Core series implements many key features in pure hardware such as; IPv4, ARP, ICMP, VLAN, Jumbo frames up to 9 KBytes plus many more options. The standard Core supports up to 256 concurrent TCP sessions which can easily be scaled down or up depending upon available FPGA resources and user design requirements.
In addition, protocols filtering with partial or full bypass are supported. Many internal or external memory interfaces e.g., DDR, QDR are also available. Many TCP protocol and several performance level features are fully customizable as design options, e.g., scalable size of Rx and Tx FIFOs, more than 256 sessions, multiple TOEs in a single FPGA or adjacent FPGAs, selective ACKs, Slow Start etc.
This Nano-TOE is also pre-integrated with Intilop's high performance 20-nanosecond EMAC as an IP-Core bundle that delivers unprecedented lowest industry total latency of 96 nanoseconds for the EMAC’s input to TOE User_FIFO out. Moreover, the Nano-TOE is also available as pre-integrated full system with Intilop’s PCIe/DMA IP block ported and tested on several FPGA platforms. An optimized version of which can deliver a 20G total system wire to user-space latency close to 1 µs. Finally, the Nano-TOE’s scalable architecture is designed to allow seamless upgrade/migration path to 40G networks and beyond.