In SDR, imec notes, the ADC needs high speed, high resolution and high power efficiency in a dynamic solution, supporting high, as well as low bandwidth standards. The pipelined SAR ADC developed by imec and Renesas Electronics achieves a peak SNDR (signal to noise distortion ratio) of 70.7 dB at a speed as high as 200 Msamples/sec while consuming only 2.3 mW at 0.9V supply voltage. The implementation in 28 nm digital CMOS not only adds to its area and power efficiency, but also supports digitalisation of the radio.
“This novel ADC architecture is an important achievement in imec's R&D program on future wireless technologies, focusing on the development of highly flexible software-defined radios that support high bandwidth and well as low bandwidth standards,” commented Liesbet Van der Perre, programme director, wireless technologies at imec. “The architecture is based on prior groundbreaking ADC designs from imec, exploiting the opportunities of modern advanced CMOS technologies. Scaling toward smaller technology nodes will result in an even better performance of the ADC.”
Interested companies have access to imec’s ADC designs by joining imec’s industrial affiliation program, or through IP licensing.