The TSMC 40 nm LP 32-bit DDR3/3L/LPDDR2 interface features a data rate of up to 800 Mbps while providing the automated traffic-based power management and efficiency critical to the ultrabook, tablet and smartphone markets. Fully compliant with the latest published specifications from JEDEC, the Cadence IP core for DDR3/3L/LPDDR2 memory enabled Nufront to reduce design risk and speed development of their chipset.
“Our third-generation dual core mobile computing chip, the NS115 delivers the performance, power efficiency and quality required by the tablet and smartphone market. It was selected for use in tablets from several local OEMs that were recently demonstrated at the Hong Kong Electronics Fair,” said Rock Yang, vice president of marketing, Nufront. “Cadence has developed an innovative, high-quality DDR3/3L/LPDDR2 IP core architecture that gives us the configuration flexibility necessary to meet the specific needs of our customers.”
The Cadence Design IP for DDR3/3L/LPDDR2 supports key capabilities required by high-performance, low power mobile computing applications to reduce risk and speed time-to-market. The Cadence DDR memory interface IP has been licensed for use in over 400 designs. Like its Cadence counterparts for other DDR standards like DDR4 and LPDDR3, the DDR3/DDR3L/LPDDR2 solution was architected to provide designers with the ability to configure the memory interface IP for optimal performance, power and area requirements.
“Our Cadence DDR Memory IP solution provides customers the system-specific combination of performance, power and configurability along with the ease-of-integration necessary to implement the DDR interface in their SoCs,” said Marc Greenberg, product marketing director, SoC Realization Group, Cadence. “The Nufront design team seamlessly integrated our IP into their design with minimal design risk thanks to our proven memory IP controller and PHY solutions and our commitment to ensuring our customer’s silicon success.”
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