The ADS5295 uses less than 80 mW per channel, which diminishes board heat and power dissipation in higher-channel-density applications. It incorporates TI’s unique digital processing block, which combines commonly used digital functions to help improve signal-to-noise ratio (SNR) and filter harmonics while reducing output data rate for narrow-band applications. The ADS5295 can be used in phase-array architecture systems with higher channel counts, such as ultrasound, security x-ray and non-destructive testing (NDT) applications.
Using only 80 mW-per-channel at 100 MSPS and eight channels, it enables designers to increase channel count without increasing power dissipation high-density applications, while still achieving a low noise of 71 decibel full scale (dBFS) SNR. The integrated digital processing block integrates commonly used digital functions, such as a low-frequency noise suppression mode, digital filtering options and programmable mapping of low-voltage differential signaling (LVDS) output pins. This lowers FPGA cost and simplifies LVDS output routing, reducing the number of printed circuit board (PCB) layers and bill of materials cost. The device also outputs data over one or two wires of LVDS pins per channel, reducing the number of interface lines. This creates a two-wire interface, which keeps the serial data rate low to further reduce FPGA cost.
An evaluation module (EVM) is available to test the ADS5295 under a variety of conditions. The ADS5295EVM can be purchased today for US$299. An IBIS model to verify board signal integrity requirements is also available.
The ADS5295 is available now in an 80-pin HTQFP package for a suggested retail price of US$70 in quantities of 1,000.